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Cisco Bug: CSCvu69291 - cBR-8 - Linecard Does Not Transition Beyond 'Stdby Cold' Redundancy State While Standby

Last Modified

Sep 25, 2020

Products (1)

  • Cisco cBR Series Converged Broadband Routers

Known Affected Releases

16.10.1

Description (partial)

Symptom:
Primary CLC will not transition beyond 'Stdby Cold' redundancy state after LCHA.

cBR#show redundancy linecard all
 
               LC     My         Peer       Peer     Peer                       
 Slot Subslot  Group  State      State      Slot     Subslot  Role     Mode     
 -------------------------------------------------------------------------------
  1   -        0      Active     Unavail    0        -        Active   Primary  
  2   -        0      Active     Unavail    0        -        Active   Primary  
  3   -        0      Active     Unavail    0        -        Active   Primary  
  6   -        0      Active     Unavail    0        -        Active   Primary  
  7   -        0      Active     Unavail    0        -        Active   Primary  
  8   -        0      Active     Unavail    0        -        Active   Primary  
  9   -        0      Stdby Cold Active     0        -        Standby  Primary   <<<--- 
  0   -        0      Active     Stdby Cold 9        -        Active   Secondary

cBR#sh redundancy linecard history 
May 28 2020 01:12:56 1883267084 - st_mem(9): MY State Change, (Init) -> (Stdby Cold)
May 28 2020 01:12:56 1883267084 - st_mem(9): MY FSM execution, Init:Active:Up
May 28 2020 01:03:19 1883209392 - st_mem(9): MY FSM execution, Init:Active:Failed
May 28 2020 01:03:18 1883209281 - st_mem(9): MY State Change, (Failed) -> (Init)
May 28 2020 01:03:18 1883209281 - st_mem(9): MY FSM execution, Failed:Active:Reset
May 28 2020 01:03:18 1883209281 - st_mem(9): MY State Change, (Stdby Cold) -> (Failed)
May 28 2020 01:03:18 1883209281 - st_mem(9): MY FSM execution, Stdby Cold:Active:Failed
May 28 2020 01:03:18 1883209281 - st_mem(9): MY FSM execution, Stdby Cold:Active:Timer Expiry
May 28 2020 00:23:18 1882969280 - st_mem(9): MY FSM execution, Stdby Cold:Active:Cfg Dnld  <--- CLC gets stuck Stdby Cold:Active:Cfg Dnld for extended period of time
May 28 2020 00:23:18 1882969280 - st_mem(9): MY State Change, (Init) -> (Stdby Cold)
May 28 2020 00:23:18 1882969280 - st_mem(9): MY FSM execution, Init:Active:Up
May 28 2020 00:19:22 1882945620 - st_mem(9): MY FSM execution, Init:Active:Failed
May 28 2020 00:19:21 1882945508 - st_mem(9): MY State Change, (Failed) -> (Init)
May 28 2020 00:19:21 1882945508 - st_mem(9): MY FSM execution, Failed:Active:Reset
May 28 2020 00:19:21 1882945508 - st_mem(9): MY State Change, (Stdby Cold) -> (Failed)
May 28 2020 00:19:21 1882945508 - st_mem(9): MY FSM execution, Stdby Cold:Active:Failed  <--- CLC resets due to Timer Expiry, then cycles back to Stdby Cold
May 28 2020 00:19:21 1882945508 - st_mem(9): MY FSM execution, Stdby Cold:Active:Timer Expiry 
May 27 2020 23:39:21 1882705505 - st_mem(9): MY FSM execution, Stdby Cold:Active:Cfg Dnld  <--- CLC gets stuck Stdby Cold:Active:Cfg Dnld for extended period of time
May 27 2020 23:39:21 1882705505 - st_mem(9): MY State Change, (Init) -> (Stdby Cold)
May 27 2020 23:39:21 1882705505 - st_mem(9): MY FSM execution, Init:Active:Up

cBR#show platform

 Slot      Type                State                 Insert time (ago) 
 --------- ------------------- --------------------- -----------------          
 9         CBR-CCAP-LC-40G-R   ok                    4d09h            <<<--- CLC in 'ok' State and operationally okay.
 9/1       CBR-DPIC-8X10G      ok                    1w0d

Conditions:
SUPSO, then active CLC reload.
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