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Cisco Bug: CSCvt77382 - [Fretta with Phy LC]- Int. remain in dwn state even clear of error from transmission equipment

Last Modified

Sep 24, 2020

Products (1)

  • Cisco ASR 9000 Series Aggregation Services Routers

Known Affected Releases

7.0.2.BASE

Description (partial)

Symptom:
As of today, the issue observed on Potenza LC .
When int toggles from UP/down/UP than it takes ~3200 msec to bring up. 
Its suspected that Phy is taking time in clear the error.

Using Potenza LC:
On Fretta:
RP/0/RP0/CPU0:WAE1(config-if)#no shutdown
RP/0/RP0/CPU0:WAE1(config-if)#commit
Thu Apr  9 14:57:48.539 JST
 
RP/0/RP0/CPU0:WAE1(config-if)#LC/0/0/CPU0:Apr  9 14:57:51.350 JST: ifmgr[274]: %PKT_INFRA-LINK-3-UPDOWN : Interface TenGigE0/0/0/0, changed state to Up 
 
On Peer side:-
RP/0/RP0/CPU0:Apr  9 14:57:51.357 JST: ifmgr[279]: %PKT_INFRA-LINK-3-UPDOWN : Interface TenGigE0/4/0/0, changed state to Up

Using MPA-12T LC:
On Fretta:
RP/0/RP0/CPU0:WAE1(config-if)#no shutdown 
RP/0/RP0/CPU0:WAE1(config-if)#commit
Thu Apr  9 15:14:22.988 JST
 
LC/0/0/CPU0:Apr  9 15:14:23.162 JST: ifmgr[274]: %PKT_INFRA-LINK-3-UPDOWN : Interface TenGigE0/0/1/0, changed state to Up 
 
On Peer side:-
RP/0/RP0/CPU0:Apr  9 15:14:23.205 JST: ifmgr[135]: %PKT_INFRA-LINK-3-UPDOWN : Interface TenGigE0/4/0/0, changed state to Up

Conditions:
1. Interface shut & no-shut
2. When line system(optical device) flaps for convergence with-in  50ms (which is normal in line protection), line card PHY incurs ~ 3sec delay to propagate the link up signal to NPU, which results interface remain in down state for that long period of time.
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