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Cisco Bug: CSCvt64871 - CATERR after ADDDC VLS initiates on C480-M5 and C480-M5 ML

Last Modified

Jul 09, 2020

Products (1)

  • Cisco Unified Computing System

Known Affected Releases

4.0(2f)H 4.0(4e)C 4.0(4h)C

Description (partial)

A CPU CATERR (Catastrophic Error) will be logged and the system will crash/hang, and may reboot automatically.

The CIMC CATERRlog will record a Machine Check Exception on M2M iMC (integrated Memory Controller) bank(s) and the status will decode to an "M2M Timeout"
     Ex: CPU2 (0x31): IA32_MC7_STATUS (0x41d) : 0xb200000000200400

- ADDDC Sparing is the selected and running BIOS RAS feature
- The function of ADDDC, Virtual Lockstep, has initiated and spared out a failing BANK or RANK on a DIMM
- Under complex micro-architectural conditions, a memory controller that is in Virtual Lockstep (VLS) may hang on a partial write transaction. This memory controller hang will lead to a CATERR and system crash/hang
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