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Cisco Bug: CSCut31504 - DelaySim of L3 Circuits Incorrectly Derived

Last Modified

Jun 27, 2016

Products (1)

  • Cisco MATE Design

Known Affected Releases

6.1 6.2

Description (partial)

Simulated delay of a L3 circuit mistakenly ignored the delay defined on the L1 circuit path it is mapped to and is reported to be the sum of the delays on the L1 Links.

When a L3 circuit is mapped to a L1 circuit and the active L1 circuit path has a user defined delay, the reported simulated delay on the L3 circuit ignores the user defined delay and uses the sum of the delays on the L1 Links instead.
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