Cisco Bug: CSCuq96461 - ASR5500 DPC kernel crash with EDCRC error
Feb 26, 2018
- Cisco ASR 5000 Series
Known Affected Releases
15.0(22) 15.0(933) 17.0.M0.56817 22.214.171.124758 19.0.M0.60737
kernel crash on card 9 cpu1 due to EDCRC error Symptom: kernel crash, card reboot following a DFx Program CRC error detected. Can be seen on DF0 or DF1. Conditions: One of the DDF FPGAs on the DPC (or MDF on MIO) have detected a EDCRC (SEU, Single Event Upset). The EDCRC is a soft error in the DDF's configuration memory caused by a Neutron event. The configuration memory is what creates the functionality of the DDF. When the DDF detects an EDCRC we have to assume that the FPGA functionality has been compromised and a reload of the FPGA is needed. Neutron events are a known phenomenon with devices incorporating memory elements. EDCRC events are soft errors not hard errors. There is no defect in the FPGA or permanent damage when an EDCRC event occurs.
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