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Cisco Bug: CSCuo11703 - QL level flapping in Synce over copper port

Last Modified

Jan 31, 2017

Products (21)

  • Cisco ME 3600X Series Ethernet Access Switches
  • Cisco ASR 901-6CZ-FS-D Router
  • Cisco ASR 901-6CZ-F-D Router
  • Cisco ASR 901S-4SG-F-D Router
  • Cisco ME 3600X-24TS-M Switch
  • Cisco ASR 901-4C-FT-D Router
  • Cisco ASR 901S-2SG-F-AH Router
  • Cisco ASR 901-6CZ-F-A Router
  • Cisco ASR 901S-2SG-F-D Router
  • Cisco ASR 901-6CZ-FT-A Router
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Known Affected Releases


Description (partial)

The <CmdBold>show network-clock synchronization<noCmdBold> command flaps between different QL values on the same interface. Depending on the values with which the interface flaps, this could lead to triggering of network-clock selection algorithm and subsequent selection of primary reference clock for the system.

This symptom could occur when the network-clock synchronization mode is unprovisioned from automatic selection, and then the monitor interfaces are removed and a new set of interfaces are added for network-clock monitoring with automatic selection reprovisioned.
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