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Cisco Bug: CSCun83189 - FPGA hangs when changing FEC schemes under some conditions

Last Modified

Jun 21, 2020

Products (1)

  • Digital Receivers/Decoders

Known Affected Releases

nightly_build

Description (partial)

Symptom:
FEC FPGA hangs due to  invalid L/D matrix during FEC scheme change.

Conditions:
enter a valid L/D matrix for block aligned scheme (which is invalid for Non-block aligned), ans change the FEC scheme.
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