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Cisco Bug: CSCua82871 - Sup2 IOFPGA and PLX PCIe Link Sees Intermittent, Correctable Errors

Last Modified

Mar 16, 2016

Products (1)

  • Cisco Nexus 7000 Series Switches

Known Affected Releases


Description (partial)

The PCIe link between the IOFPGA and the PLX PCIe switch intermittently sees correctable physical-layer errors (disparity errors, symbol-decode errors, and replay timeouts).

The errors occur only in IOFPGA revisions 1.B and earlier, which have the SEU Mitigation (SEM) IP logic enabled.  The errors occur more frequently at low-temperature and high-voltage conditions.  It has been observed that the errors occur only when the SEM IP logic is enabled and running.
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