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Cisco Bug: CSCtb82168 - Wrong output display in 'sh freq sync clock br' when no clock-int provis

Last Modified

Feb 06, 2017

Products (1)

  • Cisco ASR 9000 Series Aggregation Services Routers

Known Affected Releases


Description (partial)

Wrong output display under the 'show frequency synchronization clock-interfaces brief' when there is no clock-interfaces provisioned. 

This issue is only seen when there is no configuration on the clock-interfaces (sync 0 and sync 1).

In the example below the clock interfaces are not configured. In this case, user should ignore the info displays in the "QLrcv", "QLuse", "Pri", "QLsnd" and "Output driven by" fields.  

RP/0/RSP1/CPU0:RedOct#show fre syn clock br

Flags:  > - Up                D - Down              S - Assigned for selection
        d - SSM Disabled      s - Output squelched  L - Looped back
Node 0/RSP1/CPU0:
  Fl    Clock Interface     QLrcv  QLuse  Pri QLsnd  Output driven by
  ===== =================== ====== ====== === ====== ========================
  D     Sync0               None   Fail   100 PRC    SONET0/6/0/0
  D     Sync1               None   Fail   100 PRC    SONET0/6/0/0    
  >S    Internal0           n/a    SEC    255 n/a    n/a                     
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