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Cisco Bug: CSCta12215 - Incorrect bits are enabled in CPU_MASTER_CONTROL register

Last Modified

Jan 12, 2017

Products (1)

  • Cisco Carrier Routing System

Known Affected Releases


Description (partial)


h/w can become unstable if memory bus is driven hard


H/W respin of system controller and redefining bits used in the MASTER_CONTROL register
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